Prior to the invention, six photolithographic process steps were required to make a TFT in an array panel. FIG. 1A is a diagrammatic view of a first mask process step. According to an industry known conventional photolithographic patterning process, a beam of electromagnetic radiation is directed through a first patterned photolithographic mask. The beam is patterned by the mask and is focused to irradiate a first photo resist layer with an irradiated pattern. The patterned photo resist is washed with a developer to remove the un-irradiated pattern, followed by selective etching of the metal layer, with the patterned photo resist in place, to form a patterned gate (100) of a TFT device and a patterned bus-line conductor (102) on a substrate (104). The bus-line conductor (102) of FIG. 1 represents either a gate bus-line conductor or a data bus-line conductor.
FIG. 1B discloses the substrate (104) of FIG. 1A with an insulation layer to form the gate (100), and additional material layers (106), (108) and (110) resulting from a second mask process step. The second mask process step requires a patterned second photolithographic mask used for irradiating a corresponding second photo-resist with a pattern for selective etching, followed by selective etching with the second patterned photo resist in place. Etching results through both a semiconductor layer (108) and a successive ohmic contact layer (110) on the TFT gate insulation layer (106), to form a patterned TFT device.
FIG. 1C discloses a third mask process step that requires a third photolithographic mask for irradiation of a corresponding third photo resist with a pattern for selective etching, followed by selective etching, with the third patterned photo resist in place, to form a via hole (112) through the gate insulation layer (106) over each corresponding bus-line conductor (102).
FIG. 1D discloses a fourth mask process step. The substrate of FIG. 1C is covered by a second conductor metal layer (114). A fourth photolithographic mask is required for irradiating a corresponding fourth photo-resist with a pattern for selective etching of the second conductor metal layer (114) with a pattern of second bus-line conductor metal on the bus-line conductor (102) and on the TFT device. A notch (116) is etched through the metal layer (114) and each ohmic contact layer (110) and in the semiconductor layer (108) of each TFT device.
FIG. 1E discloses a fifth mask process step. The construction of FIG. 1D is covered by a passivation layer (118). A fifth photolithographic mask is required for irradiating a corresponding fifth photo-resist layer with a pattern for selective etching of the passivation layer with a pattern of via holes (120) exposing contact regions on the patterned, second conductor metal (114).
FIG. 1F discloses a sixth mask process step. A transparent conductive metal layer (122) covers the passivation layer (118) and enters the via holes (120) to connect with the contact regions of the patterned, second conductor metal (114). A sixth photolithographic mask is required for irradiating the transparent metal layer (122) with a pattern. The transparent metal layer (122) is selectively etched to form a pattern of pixel electrodes and storage capacitors on the passivation layer (118), and to form protection material on gate conductor pads and data conductor pads.